1. Field of the Invention
The present invention relates to the field of microelectronics. In particular, it relates to a highly integrated circuit, especially for a multi-chip module, comprising:
(a) a flat semiconductor chip with a chip area and a plurality of chip connections arranged with a first grid spacing; PA1 (b) a flat substrate with a top side and an underside and a substrate area which is greater than the chip area; PA1 (c) on the top side of the substrate a mounting area, on which the semiconductor chip is arranged; PA1 (d) the substrate projecting on all sides with a substrate edge beyond the semiconductor chip; and PA1 (e) there being provided on the top side of the substrate first connecting areas with a grid spacing which is essentially equal to the first grid spacing; and PA1 (f) the chip connections being conductively connected to the first connecting areas. PA1 the overall area required is still far greater than the active area of the Si-chip; PA1 the ICs must additionally be subjected on the wafer to a special treatment (building of so-called bumps on the IC connections in a wafer fabrication); PA1 special, expensive tools are required for mounting; and PA1 the testing and the handling must be carried on special machines. PA1 (a) on the top side of the substrate conductor tracks extend to the edges of the substrate starting from the first connecting areas; and PA1 (b) there are provided at the edges of the substrate second connecting areas which are connected to the first connecting areas by the conductor tracks. PA1 (a) applied to a substrate plate, which has an area considerably greater than the substrate area, and which contains the later substrate with the mounting area lying in the center of the area, are, inside the substrate area, the first connecting areas, and outside the substrate area, test connections with a considerably larger grid spacing, as well as conductor tracks connecting the first connecting areas to the test connections; PA1 (b) the semiconductor chip is fastened on the substrate plate inside the mounting area; PA1 (c) the chip connections are conductively connected to the first connecting areas; PA1 (d) the functioning of the semiconductor chip is fully tested by means of the test connections; and PA1 (e) the substrate is separated from the substrate plate, the conductor tracks being severed at the edges of the substrate. PA1 (a) there are provided inside the mounting area in the substrate through-metallized through-holes which conductively connect the top side of the substrate to its underside, and have on the underside contact areas in the form of bumps; PA1 (b) the through-holes are arranged with a grid spacing which is considerably larger than the first grid spacing; and PA1 (c) at least on the top side of the substrate conductor tracks extend to the through-holes starting from the first connecting areas. PA1 (a) the through-holes are made in the substrate inside the mounting area; PA1 (b) applied to the substrate are the first connecting areas, as well as conductor tracks which connect the first connecting areas to the through-holes; PA1 (c) the through-holes are through-metallized and provided on the underside with the bumps; PA1 (d) the semiconductor chip is fastened on the substrate inside the mounting area; PA1 (e) the chip connections are conductively connected to the first connecting areas; and PA1 (f) the functioning of the semiconductor chip is fully tested by means of the bumps. PA1 the IC can be fully tested dynamically before mounting (including burn-in test); PA1 the space requirement is only insignificantly greater than for the Si-chip itself; and PA1 no special tools and machines (except a wire-bonder) and no special fabrication steps during the IC production are necessary.
A highly integrated circuit of this type is known from conventional housing technology.
The invention further relates to a method for the production of such a highly integrated circuit, in which, on the top side of the substrate, conductor tracks extend to the edges of the substrate starting from the first connecting areas; and there are provided at the edges of the substrate second connecting areas which are connected to the first connecting areas by means of the conductor tracks.
Finally, the invention relates to a method for the production of such a highly integrated circuit in which there are provided inside the mounting area in the substrate through-metallized through-holes which conductively connect the top side of the substrate to its underside, and have on the underside contact areas in the form of bumps; the through-holes are arranged with a grid spacing which is considerably larger than the first grid spacing; and at least on the top side of the substrate conductor tracks extend to the through-holes starting from the first connecting areas.
2. Discussion of Background
The continued increase in miniaturization and integration in microelectronics is evidenced in the ever more complex highly integrated VLSI (Very Large Scale Integration) circuits.
Further advances into the sub-micrometer range with increased complexity at the same time leads to integrated circuits (IC) with several million transistor functions and with Si-chip areas of more than 12 mm.times.12 mm. The number of connections per IC increases over-proportionally thereby (Moore's law).
As a result of this development, problems arise above all for the housing technologies for such ICs, that is when the chips are inserted. The housings which are known and used at present, such as, for example, DIP, SO, PLCC, LCCC, PGA etc. (see in this respect: Electronics, Nov. 11 (1985), pp. 26-31) become disproportionately large for connection numbers greater than around 200 per IC and hence uneconomic and unreliable, and lead to increased delay times of the electrical signals to and from the IC.
The reasons for this lie in the requirements for the minimum spacings of the connections of such housings, which must be approximately 0.5 mm to permit solder connections to the carrier substrate (circuit board or ceramic substrate). With 200 connections, housing edge lengths of more than 25 mm thus result, so that the ratio of active chip area to the area requirement of the housing is very poor.
A potential way around this problem is the mounting of naked IC chips (without housing) on a large-area carrier substrate, it being possible to realize the electrical connections from the IC to the substrate by means of flip-chips or wire-bonding, for example.
It is advantageous here to mount several ICs on such a carrier substrate and connect them electrically in a very small space. This results in so-called multi-chip modules (MCM) or multi-chip packages (MCP). A very space-saving and reliable mounting even for ICs with more than 200 connections is achieved thereby.
However, even this housing and mounting technology has its problems: the naked ICs cannot be dynamically tested 100% before mounting, and also cannot undergo a burn-in test. Particularly users of the most up-to-date ICs find themselves often forced to accept a poor yield with these ICs. A poor yield with the ICs has, however, disastrous effects on the yield of the MCM. Thus, for example, where 5 ICs are mounted with a yield of 90% each, the overall yield of the MCM falls to values of less than 60%. It is, however, only possible to replace defective ICs on such MCMs to a limited extent, and in any case is very complex and expensive.
Another potential solution of the housing problem for the ICs is tape automated bonding (TAB). This special housing and mounting technology on a film carrier makes it possible to fully test the ICs before insertion (see in this respect: Electronic Packaging & Production, December, 1984, pp. 34-39).
However, even the TAB technology has a range of serious disadvantages, such as, for example:
TAB is therefore only suitable for selected applications where, for example, high numbers or a very small design height are required.